1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as an EEPROM (Electrically Erasable/Programmable Read Only Memory).
2. Description of the Prior Art
As to a memory transistor in an EEPROM, conventionally, a transistor which has a following gate structure is applied. More specifically, an electrically insulated floating gate is formed over a tunnel oxide film superposed on a surface of a semiconductor substrate, and a control gate is further superposed with an underlying insulating film above the floating gate. For example, in an N-channel transistor, hot electrons produced in the vicinity of a drain are caused to pass through the tunnel oxide film and be injected into the floating gate to write data. Then, electrons accumulated in the floating gate are pulled out from a source side to erase data. The threshold voltage of the transistor varies from a state where electrons are accumulated in the floating gate to a state where no electrons are accumulated therein. Then, a sense voltage of a medium value is applied to the control gate to examine whether the transistor turns on or maintains an OFF-state, and eventually the data reading is effected.
EEPROMs utilizing a memory transistor having the floating gate as mentioned above can be classified into a full-future type and a flash type. As to the full-future type, a select transistor is provided in a memory transistor of each cell to write, erase or read data in or from each cell independently. As to the flash type, the data writing and the data reading are carried out in each individual cell while the erasing is carried out in all the cells en bloc.
However, since the full-future type one has a select transistor provided in each individual cell, each cell accordingly covers a larger area, which causes a difficulty in high integration. Hence, in recent years, development of the flash type one has been advanced more.
Typically, a memory transistor in the flash type EEPROM is of stack gate structure as shown in FIG. 13. As can be seen, a P-well 62 is formed in an N-type silicon substrate 61, and a tunnel oxide film 63, a floating gate 64, an insulating film 65, and a control gate 66 are laminated in this order on and above the P-well 62. In the P-well 62 on opposite sides of the tunnel oxide film 63, an N.sup.+ -type source diffusion layer 67 and an N.sup.+ -type drain diffusion layer 68 are formed. Moreover, a P.sup.+ -type diffusion layer 69 is formed around the drain diffusion layer 68. The P.sup.+ -type diffusion layer is useful to concentrate an electric field in the boundary region between the drain diffusion layer 68 and the P-well 63 so as to enhance a hot electron producing efficiency. In the vicinity of the source diffusion layer 67, an N.sup.- -type diffusion layer 70 is formed. The N.sup.- -type diffusion layer 70 softens a variation in an impurity concentration in the boundary region between the source diffusion layer 67 and the P-well 62 so as to make a structure of high sustain voltage in the boundary region.
In such a structure, applying positive high level voltage to a control gate G and a drain D and applying ground potential to a source S, hot electrons are produced in the vicinity of the drain diffusion layer 68. The hot electrons pass through the tunnel oxide film 63 and are injected into the floating gate 64. In this way, the data writing is attained.
In erasing data, ground potential is applied to the gate G, and erasing voltage is applied to the source S. Consequently, electric charges in the floating gate 64 are pulled out into the source diffusion layer 67 according to a tunnel effect of the Fowler-Nordheim type, and thus the data erasing is accomplished.
A threshold of the transistor varies between two levels depending upon existence or absence of electrons in the floating gate 64. In reading data, a sense voltage having a voltage value in the middle of the two levels of the threshold is applied to the gate G. Then, by monitoring if a path between the source and drain is conductive, it can be found whether data is being written or being erased, and thus, the data reading is accomplished.
In the EEPROM, memory transistors as mentioned above are disposed in a matrix manner, where sources S of those transistors are commonly connected. In erasing data, the ground potential is applied to all word lines connected to gates G while positive voltage is applied to the sources S commonly connected, and thus, the data erasing is performed in all the cells en bloc. Such a stack gate structure flash type EEPROM is advantageous in integration because a single cell includes a single transistor therein.
However, in order to erase data stored in all the cells on the substrate (or all the cells in the P-well 62) en bloc, the total erasing time must be set relatively long, allowing for a cell which requires the longest time to erase signal charges. For this reason, in a cell where signal charges are erased relatively quickly, signal charges are excessively pulled out to result in overerasure so that positive charges are accumulated in a floating gate of a memory transistor in this cell. The overerasure causes a threshold of the transistor to vary from cell to cell, and this causes instability in the reading operation. In a memory transistor of a cell where overerasure has occurred, for example, a channel is formed even under a non-selected condition due to positive charges accumulated in the floating gate, and there arises the problem that current undesirably flows between the source and drain. Hence, the reading of data stored in a target cell is unreliable.
An exemplary flash type EEPROM overcoming the above-mentioned disadvantage is proposed, in which a transistor having an SISOS (Sidewall Select-Gate on the Source Side) structure as illustrated in a simple manner in FIG. 14 is applied to a memory transistor (NIKKEI MICRODEVICES, MAY 1990, pp. 72-77). In FIG. 14, corresponding components to those in FIG. 13 are designated by like reference numerals. In this structure, a sidewall spacer (SWS) of relatively small cross-sectional area is formed in self-alignment manner on a sidewall of a gate consisting of a floating gate 64 and the like on the side of a source diffusion layer 67. The SWS is used as a select gate 71 to select a cell. In reading data, positive voltage is applied to the select gate 71 to form a channel in the P-well 62 just below the select gate 71.
In such a structure, since application of voltage to the select gate 71 permits an assured selection of a cell from which data is to be read, the data reading from non-selected cells can be prevented and reliability of the reading can be secured even when the overerasure has caused a slight variation in the threshold. Additionally, since a transistor formation region occupies no excessively large area, good integration is expected.
However, in a memory device to which a transistor of an SISOS structure as mentioned above is applied, to the select gate 71 has a high electrical resistance due to its relatively small cross-sectional area. This causes the problem that speed-up of the reading is inhibited. It is not acceptable to enlarge the cross-sectional area of the select gate 71 to avoid such a disadvantage because this would enlarge an area of the substrate and would be counter to the demand for a higher integration.
Another example of the prior art technology is shown in FIG. 15. A memory transistor used in a prior art nonvolatile semiconductor memory device is named "trap type". N.sup.+ -type high concentration impurity regions are formed in a P-type semiconductor substrate 161 to define a source diffusion layer 162 and a drain diffusion layer 163. In a surface of the semiconductor substrate 161 between them, is an insulating film 164 which can trap electrons or holes. A gate 165 is formed on the insulating film 164. The insulating film 164 is made with the so-called ONO film; the insulating film 164 is composed of a sandwich construction in which a nitride film 164C is interposed between a tunnel oxide film 164A and a top oxide film 164B.
In a writing data, writing voltage V.sub.p is applied between the gate 165 and the substrate 161, so that the gate 165 becomes electrically positive. This allows electrons to pass through the tunnel oxide film 164A according to direct tunneling from the substrate 161, and they are injected into the nitride film 164C. In a data written state where the electrons are trapped in the nitride film 164C, a threshold voltage required to turn the memory transistor on takes a high level.
In an erasing data, erasing voltage V.sub.E is applied between the gate 165 and the substrate 161 so that the gate 165 becomes electrically negative. In this way, electrons in the nitride film 164C are pulled out into the substrate 161, passing through the oxide film 164A by direct tunneling. In a data erased state where no electrons are trapped in the nitride film 164C, the threshold voltage to turn the memory transistor on has a low level.
In order to read data, a sense voltage having an intermediate voltage level between the above two threshold levels in the data written and data erased states, is applied to the gate 165 while it is monitored whether the memory transistor turns on or maintains its OFF-state.
Such trap-type memory transistor EEPROMs can be classified into a full-future type and a flash type.
As to the full-future type one, since it has a select transistor in each individual cell, a cell area becomes large, and this causes a difficulty in high integration. Hence, in recent years, development of the flash ROM has been advanced more.
In order to erase data stored in all the cells in the substrate en bloc, however, the total erasing time must be set relatively long, allowing for a cell which requires the longest time to erase signal charges. For this reason, in a cell where signal charges are erased relatively quickly, signal charges are excessively pulled out to result in overerasure so that positive charges are accumulated in the insulating film 164 of a memory transistor in this cell. The overerasure causes a threshold of the transistor to vary from cell to cell, and this causes instability in reading a memory transistor of a cell where overerasure is caused, for example, a channel is formed even under non-selected condition due to positive charges accumulated in the insulating film, and there arises the problem that current undesirably flows between the source and drain. Hence, the reading of data stored in a target cell is unreliable.
3. Description of the Related Art
A way of overcoming the disadvantage as has been described is to employ with the "trap-type" memory device the above-stated SISOS structure which seems desirable to apply to a floating gate type EEPROM. Such a modified trap-type memory device is shown in a simple way in FIG. 16. In FIG. 16, like reference numerals designate corresponding components to those in FIG. 15.
In such a structure, a sidewall spacer (SWS) of relatively small cross-sectional area is formed in self-alignment manner on a sidewall of a gate comprising a insulating film 164 and the like on the side close to a source diffusion layer 162, and the SWS is used as a select gate 171 to select a cell. In reading data, positive voltage is applied to the select gate 171 to form a channel in a semiconductor substrate 161 just below the select gate 171.
In such a structure, since application of a voltage to the select gate 171 permits an assured selection of a cell from which data is to be read, the data reading from non-selected cells can be prevented and reliability of the reading can be secured even when overerasure causes a slight variation in a threshold. Additionally, since a transistor formation region occupies no excessively large area, good integration is expected.
However, in a memory device to which a transistor of an SISOS structure as mentioned above is applied, since to the select gate 171 has a relatively small cross-sectional area, the select gate 171 is relatively high in electrical resistance, and as a result, there arises the problem that speed-up of the reading is inhibited. It is not acceptable to enlarge the cross-sectional area of the select gate 171 to avoid such a disadvantage because such a conduction leads to an increase in a substrate area, and it goes counter to the demand for a higher integration.
Employing either of the structures in FIGS. 15 and 16, direct tunneling from the substrate 161 is utilized to carry out the writing and the erasing, and therefore, a tunnel oxide film 164A must be thinned to some extent. However, using such a thin tunnel oxide film 164A, accumulated electric charges are likely to dissipate, and there arises the drawback that data retention is degraded.
A procedure to overcome this disadvantage is forming the tunnel oxide film 164A with a certain thickness, producing hot electrons, which can pass through a thick oxide film, in the vicinity of the drain diffusion layer 163, and injecting the hot electrons into the oxide film to conduct the data writing, or utilizing the Fowler-Nordheim tunnel effect to conduct the data erasing. However, electric charges trapped in an insulating film remain, and eventually, electrons are injected only into a region close to the drain diffusion layer 163 in the nitride film 164C. This local electron injection cannot cause so great a variation in threshold of a memory transistor, and this makes the data storing unstable.